1. Field of the Invention
This invention relates to communications between data buses and more particularly to control the flow of data units across a bus bridge and an inter-bus communications system employing same.
2. Description of Related Art
Data units are often required to be transmitted between separate buses in systems which have multiple buses or bus extensions.
An example of this occurs in a Compact PCI bus system where the Compact PCI bus is used as a medium to transfer Asynchronous Transfer Mode (ATM) cells between circuit cards in a chassis-based Compact PCI bus. This bus is limited to eight circuit cards per bus segment. PCI to PCI bridges are used to extend the number of circuit cards that can be supported in a single chassis.
In order to maximize the bandwidth of the Compact PCI bus, all circuit cards in the system transfer their outgoing ATM cells by performing a write burst of a 14 DWord ATM cell to a preprogrammed target address. Using writes to transfer data allows write posting across PCI to PCI bridges, which maximizes bandwidth utilization. If the target address is on a different bus segment than the initiator, the burst will be write posted into a buffer in the bridge. If an initiator is bursting an ATM cell across the bridge and the bridge buffer fills up, then the bridge will do a target disconnect even if the ATM cell has not been completely transferred. An arbiter in the bridge may grant the bus to the next initiator which will write a complete ATM cell over top of the partial ATM cell that is already in the buffer. The initiator that was disconnected will finish sending its ATM cell over top of the partial ATM cell that is already in the buffer, when it is next granted the bus. If all of the cells crossing the bridge were to the same target address, the cells would be corrupted when they arrive at the target because of the disconnect that happened while crossing the bridge.
Certain circuit cards in the system, such as modems and cell multiplexers, have a single FIFO target buffer. In order for these cards to operate properly, the 14 DWord burst must be written into the FIFO target buffer as complete cells and not as partial cells, ie., the ATM cells must arrive in their entirety and not be broken up.
Consequently, target disconnects must be prevented when data from multiple initiators intended for a single target crosses a PCI to PCI bridge to ensure that ATM cells arrive intact.
What would be desirable therefore is a way of controlling the flow of data units such as ATM cells across a bus bridge and a system which employs such flow control to avoid corrupted cells and loss of information. The present invention addresses this need.